A Sizing Methodology for the Charge Noise Reduction of A Comparator

We present a methodology to reduce the charge injection noise for an offset-free comparator, so as to achieve a higher resolution. Our method incorporates an algorithm that automatically searches for the optimal transistor sizes of a switch in the comparator. The values of this methodology are in two aspects. First of all, it takes away from designers the burden of sizing the transistors. Secondly, it is fully automatic and could ease the technology migration process. Experimental results show that the resolution of the comparator could be improved by an order of magnitude through this methodology.